Integrated circuit packaging is a crucial step in the process of providing small and highly performing semiconductor devices. As such, it has a significant effect on the appearance and function of end-user devices, from computers to cell phones to embedded processors. As in most electronics, the trend is to make semiconductor devices smaller, more powerful, and less costly. Integrated circuit (IC) packaging has evolved through multiple types of packaging technologies including, for example, system in package, package on package, chips first packaging, and so forth. These packaging technologies provide benefits in terms of high levels of integration, more functionality, space and weight savings, and commensurate cost savings.
System in package is a technology that allows the placement of several integrated circuits in one package, providing a complete set of device electronics in a small area. Package on package places one package on top of another for greater integration complexity and interconnect density. System in package and package on package techniques typically use wire bonding to connect the IC die and the package. Unfortunately, although wire bonding is a useful packaging technique, the wires take up valuable board space. Accordingly, flip chip techniques have been developed to eliminate wire bonding. In a flip chip process, an IC die is connected face-down to a board or substrate using ball grid array or other conductive bumps. This technique eliminates wire bonds, increases speeds and reduces size.
Chips-first packaging has been developed to counter the limitations of wire bonding and some ball grid array techniques. One chips-first packaging technique entails mounting the IC die or dies face down to a releasable adhesive and then encapsulating them to form an extended surface around the die. The resulting array structure is released from the substrate and the interconnect circuitry is built above the IC die and the extended surface. The interconnect is formed to the IC die as an integral part of the processing of the circuit board, thus eliminating the need for wire bonds, tape-automated bonds (TABs), or solder bumps.
FIG. 1 shows a side view of an IC die 20 undergoing a prior art chips-first packaging process. In chips-first packaging, the bare IC dies, represented by IC die 20, are typically encapsulated with a molding material 22 to form the protective package prior to building the interconnect circuitry above them. Encapsulation of IC die 20 protects it from conditions which may degrade it and allows IC die 20 to be transported, handled, and readily configured with other components. Encapsulation can also extend the surface of IC die 20, creating a platform for the redistribution of circuitry above IC die 20. This effectively makes the chip layout larger so it can be bonded to a coarser pitch circuit board. Encapsulation entails attaching the IC die 20 with its active surface 24 face down on an adhesive 26 to hold it in place. Active surface 24 of IC die 20 refers to that side of IC die 20 having bond pads 28. IC die 20 is placed in a mold, encapsulated with molding material 22 (such as a filled epoxy resin), and molding material 22 is then cured.
Unfortunately, variations in a surface 30 of adhesive 26 and mechanical placement occasionally leave gaps under IC die 20. These gaps can result in leakage, referred to herein as resin bleeding, of molding material 22 under IC die 20. This molding material 22 can then undesirably coat bond pads 28. During the cure process, molding material 22 becomes permanently attached to bond pads 28 resulting in open circuits and rendering IC die 20 useless.
A number of approaches have been tried in an attempt to solve the resin bleeding problem. For example, some prior art techniques use wells, trenches or dams around the IC die to prevent resin bleed. Others use lead frame and mold features, and high clamping force to prevent resin bleed onto the exposed bond pads of an IC package. Still others use a seal ring around the outer perimeter of the IC die or a sacrificial layer covering the bond pads that can later be removed. Unfortunately, these prior art techniques result in increased complexity and require additional design and processing steps, thus driving up cost and introducing the probability of reliability issues. Accordingly, what is needed is a method for effectively protecting bond pads of an IC die from resin bleed when undergoing chips-first packaging that can be readily implemented in existing packaging methodologies.